View M28F420_2165895.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ai01130c 18 a0-a17 w dq0-dq14 v pp v cc m28f410 M28F420 g e v ss 15 rp byte dq15a-1 figure 1. logic diagram march 1995 m28f410 M28F420 4 megabit (x8 or x16, block erase) flash memory preliminary data dual x8 and x16 organization small size plastic packages tsop56 and so44 memory erase in blocks ? one 16k byte or 8k word boot block (top or bottom location) with hardware write and erase protection ? two 8k byte or 4k word key parameter blocks ? one 96k byte or 48k word main block ? three 128k byte or 64k word main blocks 5v 10% supply voltage 12v 5% programming voltage 100,000 program/erase cycles program/erase controller automatic static mode low power consumption ?60 a typical in standby ? 0.2 a typical in deep power down ? 20/25ma typical operating consumption (byte/word) high speed access time: 70ns extended temperature ranges a0-a17 address inputs dq0-dq7 data input / outputs dq8- dq14 data input / outputs dq15a-1 data input/output or address input e chip enable g output enable w write enable byte byte/word organization rp reset/power down/boot block unlock v pp program & erase supply voltage v cc supply voltage table 1. signal names this is preliminary infor mationon a new product now in developmen t or undergoing evaluation. details are subject to change without notice. 44 1 so44 (m) tsop56 (n) 14 x 20mm 1/38
v ss dq9 dq2 du nc e a3 a2 a8 a16 a15 nc dq5 nc nc g byte dq4 dq10 dq3 v cc v cc dq12 nc w nc nc v pp rp ai01132c m28f410 M28F420 (normal) 14 1 15 28 29 42 43 56 nc a13 a14 nc dq15a-1 a4 nc dq11 dq0 v ss a1 a11 a12 a9 a10 dq14 dq6 dq13 dq7 a6 a17 a7 a5 dq8 dq1 a0 nc figure 2a. tsop pin connections warning: nc = not connected, du = don?t use g dq0 dq8 a3 a0 e v ss a2 a1 a13 v ss a14 a15 dq7 a12 a16 byte dq15a-1 dq5 dq2 dq3 v cc dq11 dq4 dq14 a9 w du a4 v pp rp a7 ai01133c m28f410 M28F420 8 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 dq1 dq9 a6 a5 dq6 dq13 44 39 38 37 36 35 34 33 a11 a10 dq10 21 dq12 40 43 1 42 41 a17 a8 figure 2b. so pin connections warning: du = don?t use symbol parameter value unit t a ambient operating temperature grade 1 grade 3 grade 6 0to70 ?40 to 125 ?40 to 85 c t bias temperature under bias ?50 to 125 c t stg storage temperature ?65 to 150 c v io (2, 3) input or output voltages ?0.6 to 7 v v cc supply voltage ?0.6 to 7 v v a9 (2) a9 voltage ?0.6 to 13.5 v v pp (2) program supply voltage, during erase or programming ?0.6 to 14 v v rp (2) rp voltage ?0.6 to 13.5 v notes: 1. except for the rating ?operating temperature range?, stresses above those listed in the table ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the sgs-thomson sure program and other relevant quality documents. 2. minimum voltage may undershoot to ?2v during transition and for less than 20ns. 3. maximum dc voltage on i/o is v cc + 0.5v, overshoot to 7v allowed for less than 20ns. table 2. absolute maximum ratings (1) 2/38 m28f410, M28F420
operation e g w rp byte dq0 - dq7 dq8 - dq14 dq15a-1 read word v il v il v ih v ih v ih data output data output data output read byte v il v il v ih v ih v il data output hi-z address input write word v il v ih v il v ih v ih data input data input data input write byte v il v ih v il v ih v il data input hi-z address input output disable v il v ih v ih v ih x hi-z hi-z hi-z standby v ih xxv ih x hi-z hi-z hi-z power down x x x v il x hi-z hi-z hi-z note: x=v il or v ih ,v pp =v ppl or v pph table 3. operations description the m28f410 and M28F420 flash memories are non-volatile memories that may be erased electrically at the block level and programmed by byte or word. the interface is directly compatible with most microprocessors. so44 and tsop56 packages are used. organization the organization, as 512k x 8 or 256k x 16, is selectable by an external byte signal. when byte is low and the x8 organization is selected, the data input/outputsignal dq15 acts as address line a-1 and selects the lower or upper byte of the memory word for output on dq0-dq7, dq8-dq14 remain high impedance. when byte is high the memory uses the address inputs a0-a17 and the data input/outputsdq0-dq15. memory control is provided by chip enable, output enable and write enable inputs. a reset/power down/boot block unlock, tri-level input, places the memory in deep power down, normal operation or enables pro- gramming and erasure of the boot block. organi- sation code device e g w byte a0 a9 a1-a8 & a10-a17 dq0 - dq7 dq8 - dq14 dq15 a-1 word- wide manufact. code v il v il v ih v ih v il v id don?t care 20h 00h 0 device code m28f410 v il v il v ih v ih v ih v id don?t care 0f2h 00h 0 M28F420 v il v il v ih v ih v ih v id don?t care 0fah 00h 0 byte- wide manufact. code v il v il v ih v il v il v id don?t care 20h hi-z don?t care device code m28f410 v il v il v ih v il v ih v id don?t care 0f2h hi-z don?t care M28F420 v il v il v ih v il v ih v id don?t care 0fah hi-z don?t care note: rp = v ih table 4. electronic signature 3/38 m28f410, M28F420
mne- monic instruction cycles 1st cycle 2nd cycle operation address (1) data (4) operation address data rd read memory array 1+ write x 0ffh read (2) read address data rsr read status register 1+ write x 70h read (2) x status register rsig read electronic signature 3 write x 90h read (2) signature adress (3) signature ee erase 2 write x 20h write block address 0d0h pg program 2 write x 40h or 10h write address data input clrs clear status register 1 write x 50h es erase suspend 1 write x 0b0h er erase resume 1 write x 0d0h notes: 1. x = don?t care. 2. the first cycle of the rd, rsr or rsig instruction is followed by read operations to read memory array, status register or electronic signature codes. any number of read cycle can occur after one command cycle. 3. signature address bit a0=v il will output manufacturer code. address bit a0=v ih will output device code. other address bits are ignored. 4. when word organization is used, upper byte is don?t care for command input. table 5. instructions hex code command 00h invalid/reserved 10h alternative program set-up 20h erase set-up 40h program set-up 50h clear status register 70h read status register 90h read electronic signature 0b0h erase suspend 0d0h erase resume/erase confirm 0ffh read array table 6. commands blocks erasure of the memories is in blocks. there are 7 blocks in the memory address space, one boot block of 16k bytes or 8k words, two ?key parame- ter blocks? of 8k bytes or 4k words, one ?main block? of 96k bytes or 48k words, and three ?main blocks?of 128kbytes or 64k words. the m28f410 memory has the boot block at the top of the mem- ory address space (3ffffh) and the M28F420 locates the boot block starting at the bottom (00000h). erasure of each block takes typically 1 second and each block can be programmed and erased over 100,000 cycles. the boot block is hardware protected from acci- dental programming or erasure depending on the rp signal. program/erase commands in the boot block are executed only when rp is at 12v. block erasure may be suspended while data is read from other blocks of the memory, then resumed. bus operations six operationscan be performed by the appropriate bus cycles, read byte or word from the array, read electronic signature, output disable, standby, power down and write the command of an instruction. command interface commands can be written to a command interface (c.i.) latch to perform read, programming, erasure and to monitor the memory?s status. when power 4/38 m28f410, M28F420
mne- monic bit name logic level definition note p/ecs 7 p/e.c. status ?1? ready indicates the p/e.c. status, check during program or erase, and on completion before checking bits b4 or b5 for program or erase success ?0? busy ess 6 erase suspend status ?1? suspended on an erase suspend instruction p/ecs and ess bits are set to ?1?. ess bit remains ?1? until an erase resume instruction is given. ?0? in progress or completed es 5 erase status ?1? erase error es bit is set to ?1? if p/e.c. has applied the maximum number of erase pulses to the block without achieving an erase verify. ?0? erase success ps 4 program status ?1? program error ps bit set to ?1? if the p/e.c. has failed to program a byte or word. ?0? program success vpps 3 v pp status ?1? v pp low, abort vpps bit is set if the v pp voltage is below v pph (min) when a program or erase instruction has been executed. ?0? v pp ok 2 reserved 1 reserved 0 reserved notes: logic level ?1? is high, ?0? is low. table 7. status register is first applied, on exit from power down or if v cc falls below v lko , the command interface is reset to read memory array. instructions and commands eight instructions are defined to perform read memory array, read status register, read elec- tronic signature, erase, program, clear status register, erase suspend and erase resume. an internalprogram/erasecontroller (p/e.c.) handles all timing and verification of the program and erase instructions and provides status bits to indicate its operation and exit status. instructions are com- posed of a first command write operation followed by either second command write, to confirm the commands for programming or erase, or a read operationto read data from the array, the electronic signature or the status register. for added data protection, the instructions for byte or word program and block erase consist of two commands that are written to the memory and which start the automatic p/e.c. operation. byte or word programming takes typically 9 s, block erase typically 1 second. erasure of a memory block may be suspended in order to read data from another block and then resumed. a status register may be read at any time, including during the programming or erase cycles, to monitor the progress of the operation. power saving the m28f410 and M28F420 have a number of power saving features. a cmos standby mode is entered when the chip enable e and the re- set/power down (rp) signals are at v cc , when the supply current drops to typically 60 a. a deep power down mode is enabled when the re- set/power down (rp) signal is at v ss , when the supply current drops to typically 0.2 a. the time required to awake from the deep power down mode is 300ns maximum, with instructions to the c.i. recognised after only 210ns. 5/38 m28f410, M28F420
sram interface levels eprom interface levels input rise and fall times 10ns 10ns input pulse voltages 0 to 3v 0.45v to 2.4v input and output timing ref. voltages 1.5v 0.8v and 2v table 8. ac measurement conditions ai01275 3v sram interface 0v 1.5v 2.4v eprom interface 0.45v 2.0v 0.8v figure 3. ac testing input output waveform ai01276 1.3v out c l = 30pf or 100pf c l = 30pf for sram interface c l = 100pf for eprom interface c l includes jig capacitance 3.3k 1n914 device under test figure 4. ac testing load circuit symbol parameter test condition min max unit c in input capacitance v in =0v 6 pf c out output capacitance v out =0v 12 pf note: 1. sampled only, not 100% tested. table 9. capacitance (1) (t a =25 c, f = 1 mhz ) device operation signal descriptions a0-a17 address inputs. the address signals, inputs for the memory array, are latched during a write operation. a9 address input is also used for the electronic signature operation. when a9 is raised to 12v the electronic signature may be read. the a0 signal is used to read two words or bytes, when a0 is low the manufacturercode is read and when a0 is high the device code. when byte is low dq0-dq7 output the codes and dq8-dq15 are don?t care, when byte is high dq0-dq7 output the codes and dq8-dq15 output 00h. dq0-dq7 data input/outputs. the data inputs, a byte or the lower byte of a word to be programmed or a command to the c.i., are latched when both chip enable e and write enable w are active. the data output from the memory array, the electronic signature or status register is valid when chip enable e and output enable g are active. the output is high impedance when the chip is dese- lected or the outputs are disabled. dq8-dq14 and dq15a-1 data input/outputs. these input/outputs are used in the word-wide organization. when byte is high for the most significant byte of the input or output, functioning as described for dq0-dq7 above. when byte is low, dq8-dq14 are high impedance, dq15a-1 is the address a-1 input. 6/38 m28f410, M28F420
symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 10 a i cc (1, 3) supply current (read byte-wide) ttl e = v il , f = 10mhz, i out = 0ma 50 ma i cc (1, 3) supply current (read word-wide) ttl e = v il , f = 10mhz, i out = 0ma 55 ma i cc (1, 3) supply current (read byte-wide) cmos e = v ss , f = 10mhz, i out = 0ma 45 ma supply current (read word-wide) cmos e=v ss , f = 10mhz, i out = 0ma 50 ma i cc1 (3) supply current (standby) ttl e = v ih ,rp =v ih 3ma supply current (standby) cmos e=v cc 0.2v, rp = v cc 0.2v, byte = v cc 0.2v or v ss 100 a i cc2 (3) supply current (power down) rp = v ss 0.2v 5 a i cc3 supply current (program byte-wide) byte program in progress 50 ma supply current (program word-wide) word program in progress 60 ma i cc4 supply current (erase) erase in progress 30 ma i cc5 (2) supply current (erase suspend) e = v ih , erase suspended 10 ma i pp program current (read or standby) v pp >v cc 200 a i pp1 program leakage current (read or standby) v pp v cc 10 a i pp2 program current (power down) rp = v ss 0.2v 5 a i pp3 program current (program byte-wide) byte program in progress 30 ma i pp3 program current (program word-wide) word program in progress 40 ma i pp4 program current (erase) erase in progress 30 ma i pp5 program current (erase suspend) erase suspended 200 a v il input low voltage ?0.5 0.8 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 5.8ma 0.45 v v oh output high voltage i oh = ?2.5ma 2.4 v v ppl program voltage (normal operation) 0 6.5 v v pph program voltage (program or erase operations) 11.4 12.6 v v id a9 voltage (electronic signature) 11.4 13 v i id a9 current (electronic signature) a9 = v id 500 a v lko supply voltage (erase and program lock-out) 2v v hh input voltage (rp, boot unlock) boot block program or erase 11.4 13 v notes: 1. automatic power saving reduces i cc to 8ma typical in static operation. 2. current increases to i cc +i cc5 during a read operation. 3. cmos levels v cc 0.2v and v ss 0.2v. ttl levels v ih and v il . table 10. dc characteristics (t a = 0 to 70 c; v cc =5v 10% or 5v 5% ; v pp = 12v 5%) 7/38 m28f410, M28F420
symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 10 a i cc (1, 3) supply current (read byte-wide) ttl e = v il , f = 10mhz, i out = 0ma 65 ma i cc (1, 3) supply current (read word-wide) ttl e = v il , f = 10mhz, i out = 0ma 70 ma i cc (1, 3) supply current (read byte-wide) cmos e = v ss , f = 10mhz, i out = 0ma 60 ma supply current (read word-wide) cmos e=v ss , f = 10mhz, i out = 0ma 65 ma i cc1 (3) supply current (standby) ttl e = v ih ,rp=v ih 3ma supply current (standby) cmos e=v cc 0.2v, rp = v cc 0.2v, byte = v cc 0.2v or v ss 100 a i cc2 (3) supply current (power down) rp = v ss 0.2v 8 a i cc3 supply current (program byte-wide) byte program in progress 50 ma supply current (program word-wide) word program in progress 60 ma i cc4 supply current (erase) erase in progress 30 ma i cc5 (2) supply current (erase suspend) e = v ih , erase suspended 10 ma i pp program current (read or standby) v pp >v cc 200 a i pp1 program leakage current (read or standby) v pp v cc 15 a i pp2 program current (power down) rp = v ss 0.2v 5 a i pp3 program current (program byte-wide) byte program in progress 30 ma i pp3 program current (program word-wide) word program in progress 40 ma i pp4 program current (erase) erase in progress 30 ma i pp5 program current (erase suspend) erase suspended 200 a v il input low voltage ?0.5 0.8 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 5.8ma 0.45 v v oh output high voltage i oh = ?2.5ma 2.4 v v ppl program voltage (normal operation) 0 6.5 v v pph program voltage (program or erase operations) 11.4 12.6 v v id a9 voltage (electronic signature) 11.4 13 v i id a9 current (electronic signature) a9 = v id 500 a v lko supply voltage (erase and program lock-out) 2v v hh input voltage (rp, boot unlock) boot block program or erase 11.4 13 v notes: 1. automatic power saving reduces i cc to 8ma typical in static operation. 2. current increases to i cc +i cc5 during a read operation. 3. cmos levels v cc 0.2v and v ss 0.2v. ttl levels v ih and v il . table 11. dc characteristics (t a = ?40 to 85 c; v cc =5v 10% or 5v 5% ; v pp = 12v 5%) 8/38 m28f410, M28F420
symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 10 a i cc (1, 3) supply current (read byte-wide) ttl e = v il , f = 10mhz, i out = 0ma 65 ma i cc (1, 3) supply current (read word-wide) ttl e = v il , f = 10mhz, i out = 0ma 70 ma i cc (1, 3) supply current (read byte-wide) cmos e = v ss , f = 10mhz, i out = 0ma 60 ma supply current (read word-wide) cmos e=v ss , f = 10mhz, i out = 0ma 65 ma i cc1 (3) supply current (standby) ttl e = v ih ,rp=v ih 3ma supply current (standby) cmos e=v cc 0.2v, rp = v cc 0.2v, byte = v cc 0.2v or v ss 130 a i cc2 (3) supply current (power down) rp = v ss 0.2v 80 a i cc3 supply current (program byte-wide) byte program in progress 50 ma supply current (program word-wide) word program in progress 60 ma i cc4 supply current (erase) erase in progress 30 ma i cc5 (2) supply current (erase suspend) e = v ih , erase suspended 10 ma i pp program current (read or standby) v pp >v cc 200 a i pp1 program leakage current (read or standby) v pp v cc 10 a i pp2 program current (power down) rp = v ss 0.2v 5 a i pp3 program current (program byte-wide) byte program in progress 30 ma i pp3 program current (program word-wide) word program in progress 40 ma i pp4 program current (erase) erase in progress 30 ma i pp5 program current (erase suspend) erase suspended 200 a v il input low voltage ?0.5 0.8 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 5.8ma 0.45 v v oh output high voltage i oh = ?2.5ma 2.4 v v ppl program voltage (normal operation) 0 6.5 v v pph program voltage (program or erase operations) 11.4 12.6 v v id a9 voltage (electronic signature) 11.4 13 v i id a9 current (electronic signature) a9 = v id 500 a v lko supply voltage (erase and program lock-out) 2v v hh input voltage (rp, boot unlock) boot block program or erase 11.4 13 v notes: 1. automatic power saving reduces i cc to 8ma typical in static operation. 2. current increases to i cc +i cc5 during a read operation. 3. cmos levels v cc 0.2v and v ss 0.2v. ttl levels v ih and v il . table 12. dc characteristics (t a = ?40 to 125 c; v cc =5v 10% or 5v 5% ; v pp = 12v 5%) 9/38 m28f410, M28F420
symbol alt parameter m28f410 / 20 unit -70 -80 -100 -120 v cc =5v 5% v cc =5v 10% v cc =5v 10% v cc =5v 10% sram interface eprom interface eprom interface eprom interface min max min max min max min max t avav t rc address valid to next address valid 70 80 100 120 ns t avqv t acc address valid to output valid 70 80 100 120 ns t phqv t pwh power down high to output valid 300 300 300 300 ns t elqx (2) t lz chip enable low to output transition 0000ns t elqv (3) t ce chip enable low to output valid 70 80 100 120 ns t glqx (2) t olz output enable low to output transition 0000ns t glqv (3) t oe output enable low to output valid 35 40 45 50 ns t ehqx (2) t oh chip enable high to output transition 0000ns t ehqz (2) t hz chip enable high to output hi-z 25 30 35 35 ns t ghqx (2) t oh output enable high to output transition 0000ns t ghqz (2) t df output enable high to output hi-z 25 30 35 35 ns t axqx (2) t oh address transition to output transition 0000ns notes: 1. see figure 3 and table 8 for timing measurements. 2. sampled only, not 100% tested. 3. g may be delayed by up to t elqv -t glqv after the falling edge of e without increasing t elqv . table 13. read ac characteristics (1) (t a = 0 to 70 c or ?40 to 85 c; v pp = 12v 5%) 10/38 m28f410, M28F420
symbol alt parameter m28f410 / 20 unit -80 -90 -100 -120 v cc =5v 5% v cc =5v 10% v cc =5v 10% v cc =5v 10% sram interface eprom interface eprom interface eprom interface min max min max min max min max t avav t rc address valid to next address valid 80 90 100 120 ns t avqv t acc address valid to output valid 80 90 100 120 ns t phqv t pwh power down high to output valid 300 300 300 300 ns t elqx (2) t lz chip enable low to output transition 0000ns t elqv (3) t ce chip enable low to output valid 80 90 100 120 ns t glqx (2) t olz output enable low to output transition 0000ns t glqv (3) t oe output enable low to output valid 40 45 50 55 ns t ehqx (2) t oh chip enable high to output transition 0000ns t ehqz (2) t hz chip enable high to output hi-z 30 35 40 45 ns t ghqx (2) t oh output enable high to output transition 0000ns t ghqz (2) t df output enable high to output hi-z 30 35 40 45 ns t axqx (2) t oh address transition to output transition 0000ns notes: 1. see figure 3 and table 8 for timing measurements. 2. sampled only, not 100% tested. 3. g may be delayed by up to t elqv -t glqv after the falling edge of e without increasing t elqv . table 14. read ac characteristics (1) (t a = ?40 to 125 c; v pp = 12v 5%) 11/38 m28f410, M28F420
dq0-dq15 ai01281b valid a e rp taxqx tavav valid tghqx tghqz tehqx tehqz tavqv telqv telqx tglqv tglqx tphqv power-up and standby address valid and chip enable outputs enabled data valid standby a-1, a0-a17 g figure 5. read mode ac waveforms note: write enable (w) = high 12/38 m28f410, M28F420
symbol parameter m28f410 / 20 unit -70 -80 -100 -120 v cc =5v 5% v cc =5v 10% v cc =5v 10% v cc =5v 10% sram interface eprom interface eprom interface eprom interface min max min max min max min max t elbl chip enable low to byte low 5555ns t elbh chip enable low to byte high 5555ns t blqv (2) byte low to output valid 70 80 100 120 ns t bhqv byte high to output valid 70 80 100 120 ns t blqz byte low to output hi-z 25 30 35 35 ns notes: 1. sampled only, not 100% tested. 2. it is equal to t avqv when measured from dq15a-1 valid. table 15. byte ac characteristics (1) (t a = 0 to 70 c or ?40 to 85 c; v pp = 12v 5%) symbol parameter m28f410 / 20 unit -80 -90 -100 -120 v cc =5v 5% v cc =5v 10% v cc =5v 10% v cc =5v 10% sram interface eprom interface eprom interface eprom interface min max min max min max min max t elbl chip enable low to byte low 5555ns t elbh chip enable low to byte high 5555ns t blqv (2) byte low to output valid 80 90 100 120 ns t bhqv byte high to output valid 80 90 100 120 ns t blqz byte low to output hi-z 30 35 40 45 ns notes: 1. sampled only, not 100% tested. 2. it is equal to t avqv when measured from dq15a-1 valid. table 16. byte ac characteristics (1) (t a = ?40 to 125 c; v pp = 12v 5%) 13/38 m28f410, M28F420
a0-a17 e byte valid dq0-dq7 dq0-dq14 valid dq0-dq14 dq15a-1 valid a-1 valid dq15 valid telbh tbhqv byte read word/byte transition word read ai01282 figure 6. byte mode ac waveforms, byte low to high a0-a17 e byte valid dq0-dq14 dq0-dq14 valid dq0-dq7 dq15a-1 valid a-1 valid telbl tblqv word read word/byte transition byte read ai01283b valid dq15 tblqz hi-z figure 7. byte mode ac waveforms, byte high to low note: g low, w = high, other timings as read mode ac waveforms. note: g low, w = high, other timings as read mode ac waveforms. 14/38 m28f410, M28F420
symbol alt parameter m28f410 / 20 unit -70 -80 v cc =5v 5% v cc =5v 10% sram interface eprom interface min max min max t avav t wc write cycle time 70 80 ns t phwl t ps power down high to write enable low 210 210 ns t elwl t cs chip enable low to write enable low 0 0 ns t wlwh t wp write enable low to write enable high 50 50 ns t dvwh t ds data valid to write enable high 50 50 ns t whdx t dh write enable high to data transition 0 0 ns t wheh t ch write enable high to chip enable high 10 10 ns t whwl t wph write enable high to write enable low 20 30 ns t avwh t as address valid to write enable high 50 50 ns t phhwh (5) t phs power down vhh (boot block unlock) to write enable high 100 100 ns t vphwh (5) t vps v pp high to write enable high 100 100 ns t whax t ah write enable high to address transition 10 10 ns t whqv1 (2, 3) write enable high to output valid (word/byte program) 66 s t whqv2 (2, 3) write enable high to output valid (boot block erase) 0.3 0.3 sec t whqv3 (2) write enable high to output valid (parameter block erase) 0.3 0.3 sec t whqv4 (2) write enable high to output valid (main block erase) 0.6 0.6 sec t qvph (5) t phh output valid to reset/power down high 0 0 ns t qvvpl (5) output valid to v pp low 0 0 ns t phbr (4, 5) reset/power down high to boot block relock 100 100 ns notes: 1. see figure 3 and table 8 for timing measurements. 2. time is measured to status register read giving bit b7 = ?1?. 3. for program or erase of the boot block rp must be at v hh . 4. time required for relocking the boot block. 5. sampled only, not 100% tested. table 17a. write ac characteristics, write enable controlled (1) (t a = 0 to 70 c or ?40 to 85 c; v pp = 12v 5%) 15/38 m28f410, M28F420
symbol alt parameter m28f410 / 420 unit -100 -120 v cc =5v 10% v cc =5v 10% eprom interface eprom interface min max min max t avav t wc write cycle time 100 120 ns t phwl t ps power down high to write enable low 210 210 ns t elwl t cs chip enable low to write enable low 0 0 ns t wlwh t wp write enable low to write enable high 60 70 ns t dvwh t ds data valid to write enable high 60 60 ns t whdx t dh write enable high to data transition 0 0 ns t wheh t ch write enable high to chip enable high 10 10 ns t whwl t wph write enable high to write enable low 40 50 ns t avwh t as address valid to write enable high 60 60 ns t phhwh (5) t phs power down vhh (boot block unlock) to write enable high 100 100 ns t vphwh (5) t vps v pp high to write enable high 100 100 ns t whax t ah write enable high to address transition 10 10 ns t whqv1 (2, 3) write enable high to output valid (word/byte program) 77 s t whqv2 (2, 3) write enable high to output valid (boot block erase) 0.4 0.4 sec t whqv3 (2) write enable high to output valid (parameter block erase) 0.4 0.4 sec t whqv4 (2) write enable high to output valid (main block erase) 0.7 0.7 sec t qvph (5) t phh output valid to reset/power down high 0 0 ns t qvvpl (5) output valid to v pp low 0 0 ns t phbr (4, 5) reset/power down high to boot block relock 100 100 ns notes: 1. see figure 3 and table 8 for timing measurements. 2. time is measured to status register read giving bit b7 = ?1?. 3. for program or erase of the boot block rp must be at v hh . 4. time required for relocking the boot block. 5. sampled only, not 100% tested. table 17b. write ac characteristics, write enable controlled (1) (t a = 0 to 70 c or ?40 to 85 c; v pp = 12v 5%) 16/38 m28f410, M28F420
symbol alt parameter m28f410 / 20 unit -80 -90 v cc =5v 5% v cc =5v 10% sram interface eprom interface min max min max t avav t wc write cycle time 80 90 ns t phwl t ps power down high to write enable low 210 210 ns t elwl t cs chip enable low to write enable low 0 0 ns t wlwh t wp write enable low to write enable high 50 60 ns t dvwh t ds data valid to write enable high 50 60 ns t whdx t dh write enable high to data transition 0 0 ns t wheh t ch write enable high to chip enable high 10 10 ns t whwl t wph write enable high to write enable low 30 40 ns t avwh t as address valid to write enable high 50 60 ns t phhwh (5) t phs power down vhh (boot block unlock) to write enable high 100 100 ns t vphwh (5) t vps v pp high to write enable high 100 100 ns t whax t ah write enable high to address transition 10 10 ns t whqv1 (2, 3) write enable high to output valid (word/byte program) 67 s t whqv2 (2, 3) write enable high to output valid (boot block erase) 0.3 0.4 sec t whqv3 (2) write enable high to output valid (parameter block erase) 0.3 0.4 sec t whqv4 (2) write enable high to output valid (main block erase) 0.6 0.7 sec t qvph (5) t phh output valid to reset/power down high 0 0 ns t qvvpl (5) output valid to v pp low 0 0 ns t phbr (4, 5) reset/power down high to boot block relock 100 100 ns notes: 1. see figure 3 and table 8 for timing measurements. 2. time is measured to status register read giving bit b7 = ?1?. 3. for program or erase of the boot block rp must be at v hh . 4. time required for relocking the boot block. 5. sampled only, not 100% tested. table 18a. write ac characteristics, write enable controlled (1) (t a = ?40 to 125 c; v pp = 12v 5%) 17/38 m28f410, M28F420
symbol alt parameter m28f410 / 420 unit -100 -120 v cc =5v 10% v cc =5v 10% eprom interface eprom interface min max min max t avav t wc write cycle time 100 120 ns t phwl t ps power down high to write enable low 210 210 ns t elwl t cs chip enable low to write enable low 0 0 ns t wlwh t wp write enable low to write enable high 60 70 ns t dvwh t ds data valid to write enable high 60 60 ns t whdx t dh write enable high to data transition 0 0 ns t wheh t ch write enable high to chip enable high 10 10 ns t whwl t wph write enable high to write enable low 40 50 ns t avwh t as address valid to write enable high 60 60 ns t phhwh (5) t phs power down vhh (boot block unlock) to write enable high 100 100 ns t vphwh (5) t vps v pp high to write enable high 100 100 ns t whax t ah write enable high to address transition 10 10 ns t whqv1 (2, 3) write enable high to output valid (word/byte program) 77 s t whqv2 (2, 3) write enable high to output valid (boot block erase) 0.4 0.4 sec t whqv3 (2) write enable high to output valid (parameter block erase) 0.4 0.4 sec t whqv4 (2) write enable high to output valid (main block erase) 0.7 0.7 sec t qvph (5) t phh output valid to reset/power down high 0 0 ns t qvvpl (5) output valid to v pp low 0 0 ns t phbr (4, 5) reset/power down high to boot block relock 100 100 ns notes: 1. see figure 3 and table 8 for timing measurements. 2. time is measured to status register read giving bit b7 = ?1?. 3. for program or erase of the boot block rp must be at v hh . 4. time required for relocking the boot block. 5. sampled only, not 100% tested. table 18b. write ac characteristics, write enable controlled (1) (t a = ?40 to 125 c; v pp = 12v 5%) 18/38 m28f410, M28F420
e g w dq0-dq15 command cmd or data status register rp v pp valid a0-a17 tavav tqvph tqvvpl tawvh twhax program or erase telwl twheh twhdx tdvwh twlwh tphwl twhwl tphhwh tvphwh power-up and set-up command confirm command or data input status register read boot block unblock twhqv1,2,3,4 ai01284c figure 8. program & erase ac waveforms, w controlled note: word-wide address data shown, for byte-wide dq15 becomes a-1. command input and status register read output is on dq0-dq7 only. 19/38 m28f410, M28F420
symbol alt parameter m28f410 / 20 unit -70 -80 v cc =5v 5% v cc =5v 10% sram interface eprom interface min max min max t avav t wc write cycle time 70 80 ns t phel t ps power down high to chip enable low 210 210 ns t wlel t cs write enable low to chip enable low 0 0 ns t eleh t wp chip enable low to chip enable high 50 50 ns t dveh t ds data valid to chip enable high 50 50 ns t ehdx t dh chip enable high to data transition 0 0 ns t ehwh t ch chip enable high to write enable high 10 10 ns t ehel t wph chip enable high to chip enable low 20 30 ns t aveh t as address valid to chip enable high 50 50 ns t phheh (5) t phs power down vhh (boot block unlock) to chip enable high 100 100 ns t vpheh (5) t vps v pp high to chip enable high 100 100 ns t ehax t ah chip enable high to address transition 10 10 ns t ehqv1 (2, 3) chip enable high to output valid (word/byte program) 66 s t ehqv2 (2, 3) chip enable high to output valid (boot block erase) 0.3 0.3 sec t ehqv3 (2) chip enable high to output valid (parameter block erase) 0.3 0.3 sec t ehqv4 (2) chip enable high to output valid (main block erase) 0.6 0.6 sec t qvph (5) t phh output valid to reset/power down high 0 0 ns t qvvpl (5) output valid to v pp low 0 0 ns t phbr (4, 5) reset/power down high to boot block relock 100 100 ns notes: 1. see figure 3 and table 8 for timing measurements. 2. time is measured to status register read giving bit b7 = ?1?. 3. for program or erase of the boot block rp must be at v hh . 4. time required for relocking the boot block. 5. sampled only, not 100% tested. table 19a. write ac characteristics, chip enable controlled (1) (t a = 0 to 70 c or ?40 to 85 c; v pp = 12v 5%) 20/38 m28f410, M28F420
symbol alt parameter m28f410 / 420 unit -100 -120 v cc =5v 10% v cc =5v 10% eprom interface eprom interface min max min max t avav t wc write cycle time 100 120 ns t phel t ps power down high to chip enable low 210 210 ns t wlel t cs write enable low to chip enable low 0 0 ns t eleh t wp chip enable low to chip enable high 60 70 ns t dveh t ds data valid to chip enable high 60 60 ns t ehdx t dh chip enable high to data transition 0 0 ns t ehwh t ch chip enable high to write enable high 10 10 ns t ehel t wph chip enable high to chip enable low 40 50 ns t aveh t as address valid to chip enable high 60 60 ns t phheh (5) t phs power down vhh (boot block unlock) to chip enable high 100 100 ns t vpheh (5) t vps v pp high to chip enable high 100 100 ns t ehax t ah chip enable high to address transition 10 10 ns t ehqv1 (2, 3) chip enable high to output valid (word/byte program) 77 s t ehqv2 (2, 3) chip enable high to output valid (boot block erase) 0.4 0.4 sec t ehqv3 (2) chip enable high to output valid (parameter block erase) 0.4 0.4 sec t ehqv4 (2) chip enable high to output valid (main block erase) 0.7 0.7 sec t qvph (5) t phh output valid to reset/power down high 0 0 ns t qvvpl (5) output valid to v pp low 0 0 ns t phbr (4, 5) reset/power down high to boot block relock 100 100 ns notes: 1. see figure 3 and table 8 for timing measurements. 2. time is measured to status register read giving bit b7 = ?1?. 3. for program or erase of the boot block rp must be at v hh . 4. time required for relocking the boot block. 5. sampled only, not 100% tested. table 19b. write ac characteristics, chip enable controlled (1) (t a = 0 to 70 c or ?40 to 85 c; v pp = 12v 5%) 21/38 m28f410, M28F420
symbol alt parameter m28f410 / 20 unit -80 -90 v cc =5v 5% v cc =5v 10% sram interface eprom interface min max min max t avav t wc write cycle time 80 90 ns t phel t ps power down high to chip enable low 210 210 ns t wlel t cs write enable low to chip enable low 0 0 ns t eleh t wp chip enable low to chip enable high 50 60 ns t dveh t ds data valid to chip enable high 50 60 ns t ehdx t dh chip enable high to data transition 0 0 ns t ehwh t ch chip enable high to write enable high 10 10 ns t ehel t wph chip enable high to chip enable low 30 40 ns t aveh t as address valid to chip enable high 50 60 ns t phheh (5) t phs power down vhh (boot block unlock) to chip enable high 100 100 ns t vpheh (5) t vps v pp high to chip enable high 100 100 ns t ehax t ah chip enable high to address transition 10 10 ns t ehqv1 (2, 3) chip enable high to output valid (word/byte program) 67 s t ehqv2 (2, 3) chip enable high to output valid (boot block erase) 0.3 0.4 sec t ehqv3 (2) chip enable high to output valid (parameter block erase) 0.3 0.4 sec t ehqv4 (2) chip enable high to output valid (main block erase) 0.6 0.7 sec t qvph (5) t phh output valid to reset/power down high 0 0 ns t qvvpl (5) output valid to v pp low 0 0 ns t phbr (4, 5) reset/power down high to boot block relock 100 100 ns notes: 1. see figure 3 and table 8 for timing measurements. 2. time is measured to status register read giving bit b7 = ?1?. 3. for program or erase of the boot block rp must be at v hh . 4. time required for relocking the boot block. 5. sampled only, not 100% tested. table 20a. write ac characteristics, chip enable controlled (1) (t a = ?40 to 125 c; v pp = 12v 5%) 22/38 m28f410, M28F420
symbol alt parameter m28f410 / 420 unit -100 -120 v cc =5v 10% v cc =5v 10% eprom interface eprom interface min max min max t avav t wc write cycle time 100 120 ns t phel t ps power down high to chip enable low 210 210 ns t wlel t cs write enable low to chip enable low 0 0 ns t eleh t wp chip enable low to chip enable high 60 70 ns t dveh t ds data valid to chip enable high 60 60 ns t ehdx t dh chip enable high to data transition 0 0 ns t ehwh t ch chip enable high to write enable high 10 10 ns t ehel t wph chip enable high to chip enable low 40 50 ns t aveh t as address valid to chip enable high 60 60 ns t phheh (5) t phs power down vhh (boot block unlock) to chip enable high 100 100 ns t vpheh (5) t vps v pp high to chip enable high 100 100 ns t ehax t ah chip enable high to address transition 10 10 ns t ehqv1 (2, 3) chip enable high to output valid (word/byte program) 77 s t ehqv2 (2, 3) chip enable high to output valid (boot block erase) 0.4 0.4 sec t ehqv3 (2) chip enable high to output valid (parameter block erase) 0.4 0.4 sec t ehqv4 (2) chip enable high to output valid (main block erase) 0.7 0.7 sec t qvph (5) t phh output valid to reset/power down high 0 0 ns t qvvpl (5) output valid to v pp low 0 0 ns t phbr (4, 5) reset/power down high to boot block relock 100 100 ns notes: 1. see figure 3 and table 8 for timing measurements. 2. time is measured to status register read giving bit b7 = ?1?. 3. for program or erase of the boot block rp must be at v hh . 4. time required for relocking the boot block. 5. sampled only, not 100% tested. table 20b. write ac characteristics, chip enable controlled (1) (t a = ?40 to 125 c; v pp = 12v 5%) 23/38 m28f410, M28F420
e g dq0-dq15 command cmd or data status register rp v pp valid a0-a17 tavav tqvph tqvvpl taveh tehax program or erase twlel tehwh tehdx tdveh teleh tphel tehel tphheh tvpheh power-up and set-up command confirm command or data input status register read boot block unblock tehqv1,2,3,4 ai01285c w figure 9. program & erase ac waveforms, e controlled 24/38 m28f410, M28F420
parameter test conditions m28f410 / 420 unit min typ max main block program (byte) v pp = 12v 5% 1.2 4.2 sec main block program (word) v pp = 12v 5% 0.6 2.1 sec boot or parameter block erase v pp = 12v 5% 1 7 sec main block erase v pp = 12v 5% 2.4 14 sec table 21. word/byte program, erase times (t a = 0 to 70 c; v cc =5v 10% or 5v 5%) e chip enable. the chip enable activates the memory control logic, input buffers, decoders and sense amplifiers. e high de-selects the memory and reduces the power consumption to the standby level. e can also be used to control writing to the command register and to the memory array, while w remains at a low level. both addresses and data inputs are then latched on the rising edge of e. rp reset/power down. this is a tri-level input which locks the boot block from programming and erasure, and allows the memory to be put in deep power down. when rp is high (up to 6.5v maximum) the boot block is locked and cannot be programmed or erased. when rp is above 11.4v the boot block is unlockedfor programming or erasure. with rp low the memory is in deep power down, and if rp is within v ss +0.2v the lowest supply current is ab- sorbed. g output enable . the output enable gates the outputs through the data buffers during a read operation. w write enable. it controls writing to the com- mand register and input address and data latches. both addresses and data inputs are latched on the rising edge of w. byte byte/word organization select. this input selects either byte-wide or word-wide organization of the memory. when byte is low the memory is organized x8 or byte-wide and data input/output uses dq0-dq7 while a-1 acts as the additional, lsb, of the memory address that multiplexes the upper or lower byte. in the byte-wide organization dq8-dq14 are high impedance. when byte is high the memory is organized x16 and data in- put/output uses dq0-dq15 with the memory ad- dressed by a0-a17. v pp program supply voltage. this supply voltage is used for memory programming and erase. v pp 10% tolerance option is provided for applica- tion requiring maximum 100 write and erase cycles. v cc supply voltage. it is the main circuit supply. v ss ground. it is the reference for all voltage measurements. device operation (cont?d) parameter test conditions m28f410 / 420 unit min typ max main block program (byte) v pp = 12v 5% 1.4 5 sec main block program (word) v pp = 12v 5% 0.7 2.5 sec boot or parameter block erase v pp = 12v 5% 1.5 10.5 sec main block erase v pp = 12v 5% 3 18 sec table 22. word/byte program, erase times (t a = ?40 to 85 c or ?40 to 125 c; v cc =5v 10% or 5v 5%) 25/38 m28f410, M28F420
memory blocks the memory blocks of the m28f410 and M28F420 are shown in figure 10. the differencebetween the two productsis simply an inversion of the block map to position the boot block at the top or bottom of the memory. the selection of the boot block at the top or bottom of the memory depends on the microprocessor needs. each block of the memory can be erased sepa- rately, but only by one block at a time. the erase operation is managed by the p/e.c. but can be suspended in order to read from another block and then resumed. programming and erasure of the memory is dis- abled when the program supply is at v ppl . for successful programming and erasure the program supply must be at v pph . the boot block provides additional hardware secu- rity by use of the rp signal which must be at v hh before any program or erase operation will be executed by the p/e.c. on the boot block. operations operations are defined as specific bus cycles and signals which allow memory read, command write, output disable, standby, power down, and electronic signature read. they are shown in ta- ble 3. read. read operations are used to output the contents of the memory array, the status register or the electronic signature. both chip enable e and output enable g must be low in order to read the output of the memory. the chip enable input also provides power control and should be used for device selection. output enable should be used to gate data onto the output independentof the device selection. a read operation will output either a byte or a word depending on the byte signal level. whenbyte is low the output byte is on dq0-dq7, dq8-dq14 are hi-z and a-1 is an additional ad- dress input. when byte is high the output word is on dq0-dq15. the data read depends on the previous command written to the memory (see instructions rd, rsr and rsig). 8k boot block ai01277 3ffffh 3e000h 3dfffh 3d000h 3cfffh 3c000h 3bfffh 00000h 4k parameter block 4k parameter block 48k main block 64k main block 64k main block 64k main block 30000h 2ffffh 20000h 1ffffh 10000h 0ffffh a0-a17 word wide m28f410 top boot block 8k boot block 3ffffh 30000h 2ffffh 20000h 1ffffh 10000h 0ffffh 00000h 4k parameter block 4k parameter block 48k main block 64k main block 64k main block 64k main block 04000h 03fffh 03000h 02fffh 02000h 01fffh a0-a17 word wide M28F420 bottom boot block figure 10. memory map, word-wide addresses 26/38 m28f410, M28F420
write. write operations are used to give instruction commands to the memory or to latch input data to be programmed. a write operation is initiated when chip enable e is low and write enable w is low with output enable g high. commands, input data and addresses are latched on the rising edge of w or e. as for the read operation, when byte is low a byte is input, dq8-dq14 are ?don?t care? and a-1 is an additional address. when byte is high a word is input. output disable. the data outputs are high imped- ance when the output enable g is high with write enable w high. standby. the memory is in standby when the chip enable e is high. the power consumption is re- duced to the standby level and the outputs are high impedance, independent of the output enable g or write enable w inputs. power down. the memory is in power down when rp is low. the power consumption is reduced to the power down level, and outputs are in high impedance, independant of the chip enable e, output enable g or write enable w inputs. electronic signature. two codes identifying the manufacturer and the device can be read from the memories, the manufacturer code for sgs- thomson is 20h, and the device codes are 0f2h for the m28f410 (top boot block) and 0fah for the M28F420 (bottom boot block). these codes allow programming equipment or applications to auto- matically match their interfaceto the characteristics of the particular manufacturer?s product. the electronic signature is output by a read array operation when the voltage applied to a9 is at v id , the manufacturer code is output when the address input a0 is low and the device code when this input is high. other address inputs are ignored. the codes are output on dq0-dq7. when the byte signal is high the outputs dq8-dq15 output 00h, when low these outputs are high impedance and address input a-1 is ignored. the electronic signature can also be read, without raising a9 to v id , after giving the memory the instruction rsig (see below). instructions and commands the memories include a command interface (c.i.) which latches commands written to the memory. instructions are made up from one or more com- mands to perform memory read, read status register, read electronic signature, erase, pro- gram, clear status register, erase suspend and erase resume. these instructions require from 1 to 3 operations, the first of which is always a write operation and is followed by either a further write operation to confirm the first command or a read operation(s) to output data. a status register indicates the p/e.c. status ready or busy, the suspend/in-progress status of erase operations, the failure/success of erase and program operations and the low/correct value of the program supply voltage v pp . the p/e.c. automatically sets bits b3 to b7 and clears bit b6 & b7. it cannot clear bits b3 to b5. the register can be read by the read status register (rsr) instruction and cleared by the clear status register (clrs) instruction. the meaning of the bits b3 to b7 is shown in table 7. bits b0 to b2 are reserved for future use (and should be masked out during status checks). read (rd) instruction. the read instruction con- sists of one write operation giving the command 0ffh. subsequent read operations will read the addressed memory array content and output a byte or word depending on the level of the byte input. read status register (rsr) instruction. the read status register instruction may be given at any time, including while the program/erase con- troller is active. it consists of one write operation giving the command 70h.subsequentread opera- tions output the contents of the status register. the contents of the status register are latched on the falling edge of e or g signals, and can be read until e or g returns to its initial high level. either e or g must be toggled to v ih to update the latch. additionally, any read attempt during program or erase operation will automatically output the con- tents of the status register. read electronic signature (rsig) instruction. this instruction uses 3 operations.it consists of one write operation giving the command 90h followed by two read operations to output the manufacturer and device codes. the manufacturer code, 20h, is output when the address line a0 is low, and the device code, 0f2h for the m28f410 or 0fah for the M28F420, when a0 is high. 27/38 m28f410, M28F420
erase (ee) instruction. this instruction uses two write operations. the first command written is the erase set-up command 20h. the second com- mand is the erase confirm command 0d0h. during the input of the second command an address of the block to be erased is given and this is latched into the memory. if the second command given is not the erase confirm command then the status regis- ter bits b4 and b5 are set and the instruction aborts. read operations output the status register after erasure has started. during the execution of the erase by the p/e.c., the memory accepts only the rsr (read status reg- ister) and es (erase suspend) instructions. status register bit b7 returns ?0? while the erasure is in progress and ?1? when it has completed. after com- pletion the status register bit b5 returns ?1? if there has been an erase failure because erasure has not been verified even after the maximum number of erase cycles have been executed. status reg- ister bit b3 returns ?1? if v pp does not remain at v pph level when the erasure is attempted and/or proced- ing. v pp must be at v pph when erasing, erase should not be attempted when v pp M28F420
shows the status of the p/e.c. bit b7 = ?1? indicates that programming is completed. a full status check can be made after each byte/word or after a sequence of data has been programmed. the status check is made on bit b3 for any possible v pp error and on bit b4 for any possible programming error. erase. the memory can be erased by blocks. the program supply voltage v pp must be applied be- fore the erase instruction is given, and if the erase is of the boot block rp must also be raised to v hh to unlock the boot block. the erase sequence is started by writing an erase set-up command (20h) to the command interface, this is followed by an address in the block to be erased and the erase confirm command (0d0h). the program/erase controller automatically starts and performs the block erase, providing the v pp voltage (and the rp voltage if the erase is of the boot block) is correct. during the erase the memory status is checked by reading the status register bit b7 which shows the status of the p/e.c. bit b7 = ?1? indicates that erase is completed. a full status check can be made after the block erase by checking bit b3 for any possible v pp error, bits b5 and b6 for any command sequence errors (erase suspended) and bit b5 alone for an erase error. reset. note that after any program or erase in- struction has completed with an error indication or after any v pp transitions down to v ppl the com- mand interface must be reset by a clear status register instruction before data can be accessed. automatic power saving the m28f410 and M28F420 memories place themselves in a lower power state when not being accessed. following a read operation, after a delay equal to the memory access time, the supply current is reduced from a typical read current of 25ma (cmos inputs, word-wide organization) to less than 2ma. power down the memories provide a power down control input rp. when this signal is taken to below v ss + 0.2v all internal circuits are switched off and the supply current drops to typically 0.2 a and the program current to typically 0.1 a. if rp is taken low during a memory read operation then the memory is de- selected and the outputs become high impedance. if rp is taken low during a program or erase sequence then it is aborted and the memory con- tent is no longer valid. recovery from deep power down requires 300ns to a memory read operation, or 210ns to a com- mand write. on return from power down the status register is cleared to 00h. power up the supply voltage v cc and the program supply voltage v pp can be applied in any order. the mem- ory command interface is reset on power up to read memory array, but a negative transition of chip enable e or a change of the addresses is required to ensure valid data outputs. care must be taken to avoid writes to the memory when v cc is above v lko and v pp powers up first. writes can be inhibited by driving either e or w to v ih . the memory is disabled until rp is up to v ih . supply rails normal precautions must be taken for supply volt- age decoupling, each device in a system should have the v cc and v pp rails decoupled with a 0.1 f capacitor close to the v cc and v ss pins. the pcb trace widths should be sufficient to carry the v pp program and erase currents required. 29/38 m28f410, M28F420
write 40h command ai01278 start write address & data read status register yes no b7=1 yes no b3=0 yes no b4=0 end v pp low error (1, 2) program error (1, 2) pg instruction: ? write 40h command ? write address & data (memory enters read status state after the pg instruction) do: ? read status register (e or g must be toggled) while b7 = 1 if b3 = 0, v pp low error: ? error handler if b4 = 0, program error: ? error handler figure 11. program flow-chart and pseudo code notes: 1. status check of b3 (v pp low) and b4 (program error) can be made after each byte/word programming or after a sequence. 2. if a v pp low or program erase is found, the status register must be cleared (clrs instruction) before further p/e.c. operations. 30/38 m28f410, M28F420
write 20h command ai01279 start write block address & 0d0h command read status register yes no b7=1 yes no b3=0 yes no b4, b5 = 1 end v pp low error (1) command sequence error ee instruction: ? write 20h command ? write block address (a12-a17) & command 0d0h (memory enters read status state after the ee instruction) do: ? read status register (e or g must be toggled) if ee instruction given execute suspend erase loop while b7 = 1 if b3 = 0, v pp low error: ? error handler if b4, b5 = 0, command sequence error: ? error handler yes no b5=0 erase error (1) yes no suspend suspend loop if b5 = 0, erase error: ? error handler figure 12. erase flow-chart and pseudo code note: 1. if v pp low or erase error is found, the status register must be cleared (clrs instruction) before further p/e.c. operations. 31/38 m28f410, M28F420
write 0b0h command ai01280 start read status register yes no b7=1 yes no b6=1 erase continues erase complete write 0ffh command es instruction: ? write 0b0h command (memory enters read register state after the es instruction) do: ? read status register (e or g must be toggled) while b7 = 1 if b6 = 0, erase completed (at this point the memory wich accept only the rd or er instruction) rd instruction: ? write 0ffh command ? one o more data reads from another block write 0d0h command er instruction: ? write 0d0h command to resume erasure read data from another block figure 13. erase suspend & resume flow-chart and pseudo code 32/38 m28f410, M28F420
ai01286c byte identifier yes no 90h read status yes 70h no clear status yes 50h no program set-up yes 40h or 10h no erase set-up yes 20h no erase command error yes 0ffh wait for command write (1) read status read array program read status yes ready (2) no yes od0h no a b no figure 14. command interface and program erase controller flow-diagram (a) notes: 1. if no command is written, the command interface remains in its previous valid state. upon power-up, on exit from power-down or if v cc falls below v lko , the command interface defaults to read array mode. 2. p/e.c. status (ready or busy) is read on status register bit 7. 33/38 m28f410, M28F420
ai01287b read status yes no 70h b erase yes ready (2) no a 0b0h no read status yes ready (2) no erase suspend yes 0d0h read status read array yes erase suspended ? read status (read status) yes no (erase resume) no figure 15. command interface and program erase controller flow-diagram (b) note: 2. p/e.c. status (ready or busy) is read on status register bit 7. 34/38 m28f410, M28F420
ordering information scheme for a list of available options (v cc range, array organisation, speed, etc...) refer to the current memory shortform catalogue. for further information on any aspect of this device, please contact sgs-thomson sales office nearest to you. v cc range f5v array org. 1 top boot 2 bottom boot temp. range 1 0 to 70 c 3 ?40 to 125 c 6 ?40 to 85 c option tr tape & reel packing example: m28f410 -80 x n 1 tr speed -70 70ns -80 80ns -90 90ns -100 100ns -120 120ns power supplies blank v cc 10%, v pp 5% xv cc 5%, v pp 5% package m so44 n tsop56 14 x 20mm 35/38 m28f410, M28F420
tsop-a d1 e 1n cp b e a2 a n/2 d die c l a1 symb mm inches typ min max typ min max a 1.20 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.05 0.037 0.041 b 0.17 0.27 0.007 0.011 c 0.10 0.21 0.004 0.008 d 19.80 20.20 0.780 0.795 d1 18.30 18.50 0.720 0.728 e 13.90 14.10 0.547 0.555 e 0.50 - - 0.020 - - l 0.50 0.70 0.020 0.028 0 5 0 5 n56 56 cp 0.10 0.004 tsop56 tsop56 - 56 lead plastic thin small outline, 14 x 20mm drawing is not to scale 36/38 m28f410, M28F420
so-b e n cp b e a2 d c l a1 1 h a symb mm inches typ min max typ min max a 2.42 2.62 0.095 0.103 a1 0.22 0.23 0.009 0.010 a2 2.25 2.35 0.089 0.093 b 0.50 0.020 c 0.10 0.25 0.004 0.010 d 28.10 28.30 1.106 1.114 e 13.20 13.40 0.520 0.528 e 1.27 0.050 h 15.90 16.10 0.626 0.634 l 0.80 0.031 3 3 n44 44 cp 0.10 0.004 so44 so44 - 44 lead plastic small outline, 525 mils body width drawing is not to scale 37/38 m28f410, M28F420
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1995 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 38/38 m28f410, M28F420

▲Up To Search▲

Price & Availability of M28F420

	To Download M28F420 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .